1. Field of Invention
The current invention relates generally to apparatus, systems and methods for simulating electrical circuits. More particularly, the apparatus, systems and methods relate to simulating a portion of a circuit design. Specifically, the apparatus, systems and methods provide for simulation of a critical portion of a VLSI design to be fabricated in silicon as well as post silicon hardware debugging.
2. Description of Related Art
Large circuit designs such as those fabricated into an application specific integrated semiconductor (ASIC) can have millions of transistors and other electrical components that need to be tested. In order to produce a functioning chip, both the logic and the hardware need to be tested. Wire routes in the ASIC create inductance and capacitance that can affect voltages on components near them. Once these inductances and capacitances are known, simulation tools can create analog simulations of every component on the ASIC so that it can be more accurately tested.
Parasitic extraction is the calculation of the parasitic effects in both the electronic device and the required wiring interconnects between those devices. Parasitic values that need to be known are the geometries of electronic devices and wiring, parasitic capacitances, parasitic resistances and parasitic inductances. These types of values and parameters are often simply referred to as parasitics.
The major purpose of parasitic extraction is to create an accurate analog model of the circuit, so that detailed simulations can emulate actual digital and analog circuit responses. Digital circuit responses are often used to populate databases for signal delay and loading calculations such as: timing analysis; circuit simulation; and signal integrity analysis. Analog circuits are often run in detailed test benches to indicate if the extra extracted parasitics will still allow the designed circuit to function.
Interconnect capacitance is calculated by giving the extraction tool the following information: the top view layout of the design in the form of input polygons on a set of layers; a mapping to a set of devices and pins (from a Layout Versus Schematic run), and a cross sectional understanding of these layers. This information is used to create a set of layout wires that have added capacitors where the input polygons and cross sectional structure indicate a capacitor is needed. The output netlist contains the same set of input nets as the input design netlist and adds parasitic capacitor devices between these nets.
Interconnect resistance is calculated by giving the extraction tool the following information: the top view layout of the design in the form of input polygons on a set of layers, a mapping to a set of devices and pins, and a cross sectional understanding of these layers including the resistivity of the layers. This information is used to create a set of layout sub-wires that have added resistance between various sub-parts of the wires. The above interconnect capacitance is divided and shared amongst the sub-nodes in a proportional way. Note, that unlike interconnect capacitance, Interconnect resistance needs to add sub-nodes between the circuit elements to place these parasitic resistors. This can greatly increase the size of the extracted output netlist and can cause additional simulation problems. What is needed is a better way of simulating large circuit designs